Integrated circuit memories include static random access memory (SRAM). Many SRAM cell structures utilize six-transistor and four-transistor memory cells. The large layout areas associated with such six-transistor and four-transistor memory cells which are used in many implementations of SRAM cells has limited the design of high density SRAM devices.
Given these drawbacks, there have been attempts to build a thyristor-based memory cell to reduce layout area associated with conventional memory cells, and provide a thyristor-based memory cell having a simple layout. A thyristor is a bi-stable, three terminal device which consists of a four layer structure including a P-type anode region, an N-type base, a P-type base, and an N-type cathode region arranged in a PNPN configuration. PN junctions are formed between P-type anode region and the N-type base, between the N-type base and the P-type base, and between the P-type base and the N-type cathode region. Contacts are made to the P-type anode region, the N-type cathode region, and the P-type base coupled to the gate electrode.
FIG. 1 is a circuit schematic 100 which illustrates an array of conventional thyristor-based Random Access Memory (TRAM) cells including TRAM cell 110.
As shown in FIG. 1, TRAM cell 110 consists of a word lines 120, 130, a bit line 150, a Thin Capacitively-Coupled Thyristor (TCCT) device 160 in series with an NMOS access transistor 170. The TCCT device 160 provides an active storage element which comprises a thyristor and a capacitor coupled to the gate of the thyristor. The NMOS access transistor 170 is coupled between a cathode node 146 of the TCCT device 160 and the bit line 150. An anode node 148 of the TCCT device 160 is fixed at a positive bias. The TCCT device 160 exhibits a bi-stable current-versus-voltage (I-V) characteristic. The bi-stable current-versus-voltage (I-V) characteristic results in a wide read margin between logical one (1) and logical zero (0) data states because the on/off current ratio between two states are greater than 1×105. The bi-stable current-versus-voltage (I-V) characteristic results in good read current because at a logical one (1) data state, TCCT device 160 is in forward diode mode resulting in higher current. The T-RAM cell 110 can make it difficult to maintain good retention and disturb characteristics because the retention of the T-RAM cell 110 is sensitive to leakage currents of the NMOS access transistor 170 which are hard to control.
FIG. 2 is a circuit schematic 200 which illustrates an array of conventional Thin Capacitively-Coupled Thyristor (TCCT)-DRAM cells including TCCT-DRAM cells 210, 270. In contrast to conventional DRAM cells, which usually include a MOSFET device and a capacitor, the TCCT-DRAM cell 210 consists of a single TCCT device 260 and three controls lines including a write enable line 230, word line 240, bit line 250. The TCCT device 260 consists of a thyristor (not labeled in FIG. 2) which includes an anode node 248 connected to the bit line 250, a cathode node 246 connected to the word line 240, and a gate capacitor (not shown) connected directly above a P-base region of the thyristor to a gate line which functions as the write enable line 230. The TCCT-DRAM cell 210 is operated using basic read/write operations which include a standby mode, a write logic one (1) operation, a write logic zero (0) operation, and a read operation.
In standby mode, both bit line 250 and word line 240 are at Vdd and the stored cell data is maintained by the charge state of the P-base region of thyristor. The word line 240 functions as the word line in TCCT DRAM, and activates the TCCT cells connected along the write enable line 230. During a write logic one (1) operation, the write enable line 230 is pulsed while word line 240 is held at ground level, triggering the TCCT device 260 to latch. The bias scheme for write zero (0) operation is the same as the write one (1) operation except that the voltage applied on the bit line 250 is kept low so that the pulsing of the write enable line 230 switches the TCCT device 260 into its blocking state. During a read operation, the word line 240 is held low and the change in the voltage or the current of the bit line 250 is read into a sense amplifier.
Although the TCCT-DRAM cell 210 does not require an access transistor, operation of the TCCT-DRAM cell 210 suffers from disturbance problems such as charge loss during a write zero operation. For example, when one TCCT-DRAM cell 210 is selected for a write zero operation, a bias level on the bit line 250 must decrease to ground which, in turn, can make an unselected TCCT-DRAM cell 270 lose charge through the bit line 250.
Accordingly, there is a need for memory devices and memory cell structures which can help to resolve such issues, and methods for fabricating those memory devices and memory cell structures.